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Foto: Matthias Friel

Prozessordesign für KI-Anwendungen: Vom System zum Transistor - Einzelansicht

Veranstaltungsart Vorlesung/Übung Veranstaltungsnummer 551921
SWS 4 Semester WiSe 2022/23
Einrichtung Institut für Informatik und Computational Science   Sprache englisch
Belegungsfristen 04.10.2022 - 10.11.2022

Belegung über PULS
04.10.2022 - 10.11.2022

Belegung über PULS
Gruppe 1:
     jetzt belegen / abmelden
    Tag Zeit Rhythmus Dauer Raum Lehrperson Ausfall-/Ausweichtermine Max. Teilnehmer/-innen
Einzeltermine anzeigen
Vorlesung Mi 10:00 bis 12:00 wöchentlich 19.10.2022 bis 08.02.2023 Dr.-Ing. Stamenkovic 21.12.2022: Akademische Weihnachtsferien
28.12.2022: Akademische Weihnachtsferien
Einzeltermine anzeigen
Übung Mi 12:00 bis 14:00 wöchentlich 19.10.2022 bis 08.02.2023 Dr.-Ing. Stamenkovic 16.11.2022: 
21.12.2022: Akademische Weihnachtsferien
28.12.2022: Akademische Weihnachtsferien
Einzeltermine anzeigen
Übung Mi 12:00 bis 14:00 Einzeltermin am 16.11.2022 Dr.-Ing. Stamenkovic  

Zur Zeit keine Belegung möglich! Zuordnung wird noch geklärt.


The performance evaluation is based on an oral final exam.


The course focuses on covering all the steps (from the system-level to the transistor-level) necessary to design, model, verify, implement, and test a silicon system for artificial intelligence (AI) applications. It targets this empty space and intents to bridge the gap between system and circuit designers, technologists, and physicist. This course is aimed to help students to function knowledgeably in the area and become promising device, circuit, and system designers, who have already acquired basic knowledge of microelectronics.

The topic is tackled using configurable general-purpose processors and designing custom hardware accelerators for AI applications. The design flow starts with a functional model at system level, where major functional blocks are defined and no timing information is given. Afterwards, all the functionalities described before are mapped to hardware and will be defined down to circuit level (register-transfer level synthesis). At that point, a cycle accurate model of the system is ready for synthesis using standard CMOS logic gates (technology mapping). Once the circuit is synthesized, the physical view (layout) of hardware is created using transistors and interconnections. Functional correctness of the design has to be verified at all three (system, circuit, and transistor) levels. Finally, the system must be tested against random and systematic faults.

The detailed list of topics includes:

-        Modeling (Systems and Circuits),

-        Modeling (Logic, Simulation, and Verification),

-        Modeling (Hardware Architectures for AI Applications),

-        Implementation (Embedded Memories and RRAM),

-        Implementation (Logic Synthesis and Configurable Processors),

-        Implementation (Layout Generation),

-        Digital Testing (Defect/Fault Modeling and Test Generation),

-        Digital Testing (Embedded Memory Test and Design-for-Test).

This course includes practical examples and requires active student work.

Keine Einordnung ins Vorlesungsverzeichnis vorhanden. Veranstaltung ist aus dem Semester WiSe 2022/23 , Aktuelles Semester: SoSe 2024